`timescale 1ns/1ps

module HC595_Driver_tb();

	reg clk;
	reg rst_n;
	reg [7:0] seg;
	reg [7:0] sel;
	wire DIO;
	wire SRCLK;
	wire RCLK;
	
HC595_Driver HC595_Driver_inst(
	.clk(clk),
	.rst_n(rst_n),
	.seg(seg),
	.sel(sel),
	.DIO(DIO),
	.SRCLK(SRCLK),
	.RCLK(RCLK)
);
	initial clk = 1;
	always #10 clk = ~clk;
	
	initial begin
		sel = 8'b0000_0001;
		seg = 8'b0101_0101;
		rst_n = 0;
		#201;
		rst_n = 1;
		#5000;
		sel = 8'b0000_0010;
		seg = 8'b1010_1010;
		#5000;
		sel = 8'b1010_0101;
		seg = 8'b0000_1101;
		#5000;
		$stop;
	end
endmodule
